Agilent Technologies Inc. (NYSE: A) announced this week, a high-performance serial bit error ratio tester with advanced jitter generation capabilities for jitter-tolerance testing (J-BERT) of serial gigabit devices up to 12.5 Gb/s. The next generation of high-speed serial bus standards with data rates of 5 Gb/s and beyond is expected by 2006. The increasing speed will cause significant signal integrity and jitter issues during the design and test of next-generation serial bus devices. In addition, new transmission techniques, such as spread spectrum clocking, make device performance characterization more difficult and time-consuming. The Agilent N4903A provides calibrated jitter composition and automated jitter characterization in a single box and is compliant with the latest serial bus standards. The N4903A provides built-in and calibrated jitter composition for stressed eye testing of receivers. Automated and compliant jitter-tolerance testing covers all popular serial bus standards, such as PCI Express, SATA, Fibre Channel, FB-DIMM, CEI, Gigabit Ethernet and XFP. "Jitter-tolerance testing is the most complex and time-consuming measurement that design teams of next-generation serial devices have to deal with," said Siegfried Gross, vice president and general manager of Agilent's Digital Verification Solutions division. "With the introduction of the first and only complete, one-box jitter-tolerance test solution, Agilent continues to demonstrate its leadership in providing innovative physical layer testers for the computer, storage and networking markets." The Agilent N4903A features include the following: Built-in, calibrated, automated and compliant jitter-tolerance testing with sources for PJ, RJ, BUJ, ISI and sinusoidal interference. Supports complex data patterns of serial bus interfaces. Unpredictable traffic can be analyzed with the bit recovery mode, enabling more realistic test scenarios. Complex training sequences can be set up with the new pattern sequencer easily, simplifying the test development process. Built-in CDR, new subrate clock outputs and spread-spectrum clocking (SSC), which significantly simplify the clock setup. Accurate characterization with the cleanest eyes, 20 ps transition times and 50 mV analyzer sensitivity.